? semiconductor components industries, llc, 2001 april, 2001 rev. 5 1 publication order number: mc100ept26/d mc100ept26 3.3v1:2 fanout differential lvpecl to lvttl translator the mc100ept26 is a 1:2 fanout differential lvpecl to lvttl translator. because lvpecl (positive ecl) levels are used only +3.3 v and ground are required. the small outline 8lead package and the 1:2 fanout design of the ept26 makes it ideal for applications which require the low skew duplication of a signal in a tightly packed pc board. the v bb output allows the ept26 to be used in a singleended input mode. in this mode the v bb output is tied to the d0 input for a noninverting buffer or the d0 input for an inverting buffer. if used, the v bb pin should be bypassed to ground via a 0.01 m f capacitator. ? 1.4 ns typical propagation delay ? maximum frequency > 275 mhz typical ? the 100 series contains temperature compensation ? operating range: v cc = 3.0 v to 3.6 v with gnd = 0 v ? open input default state ? safety clamp on inputs ? 24 ma ttl outputs ? q outputs will default low with inputs open or at v ee ? v bb output device package shipping ordering information mc100ept26d so8 98 units/rail mc100ept26dr2 so8 mc100ept26dt tssop8 100 units/rail mc100ept26dtr2 tssop8 http://onsemi.com *for additional information, see application note and8002/d marking diagrams* a = assembly location l = wafer lot y = year w = work week alyw kpt26 alyw ka26 2500 tape & reel 2500 tape & reel so8 d suffix case 751 1 8 tssop8 dt suffix case 948r 1 8 1 8 1 8
mc100ept26 http://onsemi.com 2 1 2 3 45 6 7 8 q0 gnd v cc figure 1. 8lead pinout (top view) and logic diagram d q1 d v bb nc lvttl lvpecl pin description pin q0, q1 d**, d ** differential lvpecl input pair function lvttl outputs v cc v bb output reference voltage positive supply gnd ground nc no connect ** pins will default to v cc /2 when left open. attributes characteristics value internal input pulldown resistor 75 k internal input pullup resistor 37.5 k esd protection human body model machine model charged device model > 2 kv > 100 v > 2 kv moisture sensitivity, indefinite time out of drypack (note 1.) level 1 flammability rating oxygen index ul94 code v0 a 1/8o 28 to 34 transistor count 117 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d. maximum ratings (note 2.) symbol parameter condition 1 condition 2 rating units v cc positive power supply gnd = 0 v 3.8 v v in p ut voltage gnd 0 v v v 0to38 v v in input voltage gnd = 0 v v i v cc 0 to 3.8 v i bb v bb sink/source 0.5 ma ta operating temperature range 40 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 8 soic 8 soic 190 130 c/w c/w q jc thermal resistance (junction to case) std bd 8 soic 41 to 44 c/w q ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 8 tssop 8 tssop 185 140 c/w c/w q jc thermal resistance (junction to case) std bd 8 tssop 41 to 44 c/w t sol wave solder <2 to 3 sec @ 248 c 265 c 2. maximum ratings are those values beyond which device damage may occur.
mc100ept26 http://onsemi.com 3 pecl input dc characteristics v cc = 3.3 v; gnd = 0.0 v (note 3.) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit v ih input high voltage (single ended) 2075 2420 2075 2420 2075 2420 mv v il input low voltage (single ended) 1355 1675 1355 1675 1355 1675 mv v bb output voltage reference 1775 1875 1975 1775 1875 1975 1775 1875 1975 v v ihcmr input high voltage common mode range (differential) (note 4.) 2.0 3.3 2.0 3.3 2.0 3.3 v i ih input high current 150 150 150 m a i il input low current d d 0.5 150 0.5 150 0.5 150 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 3. input parameters vary 1:1 with v cc . 4. v ihcmr min varies 1:1 with gnd, v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. ttl output dc characteristics v cc = 3.3 v; gnd = 0.0 v; t a = 40 c to 85 c symbol characteristic condition min typ max unit v oh output high voltage (note 5.) i oh = 3.0 ma 2.4 v v ol output low voltage (note 5.) i ol = 24 ma 0.5 v i cch power supply current 10 20 18 ma i ccl power supply current 15 28 35 ma i os output short circuit current 50 150 ma 5. all loading with 500 ohms to gnd, cl = 20 pf. ac characteristics v cc = 3.0 v to 3.6 v; gnd = 0.0 v (note 6.) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum frequency (see figure 2. f max /jitter) 275 350 275 350 275 350 mhz t plh , t phl propagation delay to output differential (note 7.) 1.2 1.2 1.5 1.5 1.8 1.8 1.2 1.2 1.5 1.5 1.8 1.8 1.3 1.2 1.7 1.5 2.2 1.8 ns t sk+ + t sk t skpp within device skew++ within device skew devicetodevice skew (note 8.) 60 25 500 60 25 500 60 25 500 ps t jitter cycletocycle jitter (see figure 2. f max /jitter) tbd tbd tbd ps v pp input voltage swing (differential) 150 800 1200 150 800 1200 150 800 1200 mv t r t f output rise/fall times (0.8v 2.0v) q, q 330 600 900 330 600 900 330 650 900 ps 6. measured using a 750 mv source, 50% duty cycle clock source. all loading with 500 ohms to gnd. 7. reference (v cc = 3.3v 5%; gnd = 0v) 8. skews are measured between outputs under identical transitions.
mc100ept26 http://onsemi.com 4 figure 2. f max /jitter frequency (mhz) 0 500 1000 1500 2000 2500 3000 0 50 100 150 200 250 300 350 400 450 500 550 600 1 2 3 4 5 6 (jitter) v oh v ol 0.5 v v outpp (mv) jitter out ps (rms) figure 3. ttl output loading used for device evaluation ttl driver receiver qd ttl 500 gnd r l c l * * 20 pf total cap (includes fixture).
mc100ept26 http://onsemi.com 5 resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1503 eclinps i/o spice modeling kit an1504 metastability and the eclinps family an1560 low voltage eclinps spice modeling kit an1568 interfacing between lvds and ecl an1596 eclinps lite translator elt family spice i/o model kit an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8020 termination of ecl logic devices for an updated list of application notes, please see our website at http://onsemi.com.
mc100ept26 http://onsemi.com 6 package dimensions so8 d suffix plastic soic package case 75107 issue w seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 x y g m y m 0.25 (0.010) z y m 0.25 (0.010) z s x s m dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 2.90 3.10 0.114 0.122 c 0.80 1.10 0.031 0.043 d 0.05 0.15 0.002 0.006 f 0.40 0.70 0.016 0.028 g 0.65 bsc 0.026 bsc l 4.90 bsc 0.193 bsc m 0 6 0 6 seating plane pin 1 1 4 85 detail e b c d a g detail e f m l 2x l/2 u s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) t v w 0.25 (0.010) 8x ref k ident k 0.25 0.40 0.010 0.016 tssop8 dt suffix plastic tssop package case 948r02 issue a notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. terminal numbers are shown for reference only. 6. dimension a and b are to be determined at datum plane -w-.
mc100ept26 http://onsemi.com 7 notes
mc100ept26 http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc100ept26/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland
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